Publications

Selected Publications

(Updated on October 28th, 2021, from dblp)

  • 2017

    [j]   Weizhi Xu, Shouyi Yin, Zhen Zhang, Hao Dong, Rui Shi, Leibo Liu, Shaojun Wei: Reconfigurable VLSI Architecture for Real-Time 2D-to-3D Conversion. IEEE Access 5: 26604-26613 (2017)
    [j]   Leibo Liu, Yingjie Chen, Chenchen Deng, Shouyi Yin, Shaojun Wei: Implementation of in-loop filter for HEVC decoder on reconfigurable processor. IET Image Processing 11(9): 685-692 (2017)
    [j]   Shouyi Yin, Peng Ouyang, Xu Dai, Leibo Liu, Shaojun Wei: An AdaBoost-Based Face Detection System Using Parallel Configurable Architecture With Optimized Computation. IEEE Systems Journal 11(1): 260-271 (2017)
    [j]   Chenchen Deng, Leibo Liu, Yang Liu, Shouyi Yin, Shaojun Wei: PMCC: Fast and Accurate System-Level Power Modeling for Processors on Heterogeneous SoC. IEEE Trans. on Circuits and Systems 64-II(5): 540-544 (2017)
    [j]   Bo Wang, Leibo Liu, Chenchen Deng, Min Zhu, Shouyi Yin, Zhuoquan Zhou, Shaojun Wei:Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks. IEEE Trans. Information Forensics and Security 12(2): 309-322 (2017)
    [j]   Chen Yang, Leibo Liu, Kai Luo, Shouyi Yin, Shaojun Wei:CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays. IEEE Trans. Parallel Distrib. Syst. 28(1): 29-43 (2017)
    [j]   Chen Wu, Chenchen Deng, Leibo Liu, Jie Han, Jiqiang Chen, Shouyi Yin, Shaojun Wei: A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems. IEEE Trans. Parallel Distrib. Syst. 28(3): 662-676 (2017)
    [j]   Shouyi Yin, Xianqing Yao, Tianyi Lu, Dajiang Liu, Jiangyuan Gu, Leibo Liu, Shaojun Wei: Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory. IEEE Trans. Parallel Distrib. Syst. 28(9): 2471-2485 (2017)
    [j]   Guiqiang Peng, Leibo Liu, Peng Zhang, Shouyi Yin, Shaojun Wei: Low-Computing-Load, High-Parallelism Detection Method Based on Chebyshev Iteration for Massive MIMO Systems With VLSI Architecture. IEEE Trans. Signal Processing 65(14): 3775-3788 (2017)
    [j]   Fengbin Tu, Shouyi Yin, Peng Ouyang, Shibin Tang, Leibo Liu, Shaojun Wei: Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns. IEEE Trans. VLSI Syst. 25(8): 2220-2233 (2017)
    [c]  Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei: Energy-aware loops mapping on multi-vdd CGRAs without performance degradation. ASP-DAC 2017: 312-317
    [c]  Jiangyuan Gu, Shouyi Yin, Shaojun Wei:Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect. DAC 2017: 40:1-40:6
    [c]  Peng Ouyang, Shouyi Yin, Shaojun Wei: A Fast and Power Efficient Architecture to Parallelize LSTM based RNN for Cognitive Intelligence Applications. DAC 2017: 63:1-63:6
    [c]  Shouyi Yin, Zhicong Xie, Shaojun Wei: Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAM. DAC 2017: 84:1-84:6
    [c]  Jianxin Guo, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei: Bit-Width Based Resource Partitioning for CNN Acceleration on FPGA. FCCM 2017: 31
    [c]  Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei: Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only). FPGA 2017: 290
    [c]  Shouyi Yin, Dajiang Liu, Lifeng Sun, Xinhan Lin, Leibo Liu, Shaojun Wei: Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only). FPGA 2017: 295
    [c]  Peng Ouyang, Shouyi Yin, Chunxiao Xing, Leibo Liu, Shaojun Wei: A Power Efficient Architecture with Optimized Parallel Memory Accessing for Feature Generation. ACM Great Lakes Symposium on VLSI 2017: 287-292
    [c]  Zhaoshi Li, Leibo Liu, Yangdong Deng, Shouyi Yin, Yao Wang, Shaojun Wei: Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware. ISCA 2017: 575-586
    [c]  Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei: Memory fartitioning-based modulo scheduling for high-level synthesis. ISCAS 2017: 1-4
    [c]  Shouyi Yin, Dajiang Liu, Lifeng Sun, Leibo Liu, Shaojun Wei: DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach. ISCAS 2017: 1-4
    [c]  Shibin Tang, Shouyi Yin, Shixuan Zheng, Peng Ouyang, Fengbin Tu, Leiyue Yao, JinZhou Wu, Wenming Cheng, Leibo Liu, Shaojun Wei:AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs. NVMSA 2017: 1-6
    [c]  Shouyi Yin, Jinjin Duan, Peng Ouyang, Leibo Liu, Shaojun Wei: Multi-CNN and decision tree based driving behavior evaluation. SAC 2017: 1424-1429

  • 2016

    [j]   Shuang Liang, Shouyi Yin, Leibo Liu, Yike Guo, Shaojun Wei: A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration. Computer Architecture Letters 15(2): 69-72 (2016)
    [j]   Peng Ouyang, Shouyi Yin, Chenchen Deng, Leibo Liu, Shaojun Wei: A fast face detection architecture for auto-focus in smart-phones and digital cameras. SCIENCE CHINA Information Sciences 59(12): 122402:1-122402:13 (2016)
    [j]   Leibo Liu, Dong Wang, Yingjie Chen, Min Zhu, Shouyi Yin, Shaojun Wei: An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform. IEICE Transactions 99-D(5): 1285-1295 (2016)
    [j]   Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu, Shaojun Wei: Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual- Vdd CGRAs. IEEE Trans. on CAD of Integrated Circuits and Systems 35(9): 1475-1488 (2016)
    [j]   Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei: A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation. IEEE Trans. on Circuits and Systems 63-II(7): 668-672 (2016)
    [j]   Wenping Zhu, Leibo Liu, Guangli Jiang, Shouyi Yin, Shaojun Wei: A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator. IEEE Trans. Circuits Syst. Video Techn. 26(8): 1532-1543 (2016)
    [j]   Bo Wang, Leibo Liu, Chenchen Deng, Min Zhu, Shouyi Yin, Shaojun Wei:Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture. IEEE Trans. Information Forensics and Security 11(6): 1151-1164 (2016)
    [j]   Leibo Liu, Junbin Wang, Jianfeng Zhu, Chenchen Deng, Shouyi Yin, Shaojun Wei:TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions. IEEE Trans. Parallel Distrib. Syst. 27(7): 2143-2154 (2016)
    [j]   Shouyi Yin, Xinhan Lin, Leibo Liu, Shaojun Wei: Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained Reconfigurable Architectures. IEEE Trans. Parallel Distrib. Syst. 27(11): 3199-3213 (2016)
    [j]   Shouyi Yin, Dajiang Liu, Yu Peng, Leibo Liu, Shaojun Wei: Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures. IEEE Trans. VLSI Syst. 24(2): 507-520 (2016)
    [j]   Shouyi Yin, Peng Ouyang, Tianbao Chen, Leibo Liu, Shaojun Wei: A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing. IEEE Trans. VLSI Syst. 24(4): 1305-1318 (2016)
    [j]   Shouyi Yin, Xianqing Yao, Dajiang Liu, Leibo Liu, Shaojun Wei: Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures. IEEE Trans. VLSI Syst. 24(5): 1895-1908 (2016)
    [j]   Shouyi Yin, Pengcheng Zhou, Leibo Liu, Shaojun Wei: Trigger-Centric Loop Mapping on CGRAs. IEEE Trans. VLSI Syst. 24(5): 1998-2002 (2016)
    [j]   Shouyi Yin, Weizhi Xu, Jiakun Li, Leibo Liu, Shaojun Wei:CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache. IEEE Trans. VLSI Syst. 24(7): 2548-2561 (2016)
    [c]  Xinhan Lin, Shouyi Yin, Leibo Liu, Shaojun Wei: Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures. ASP-DAC 2016: 456-461
    [c]  Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei: Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays. DAC 2016: 64:1-64:6
    [c]  Shouyi Yin, Zhicong Xie, Chenyue Meng, Leibo Liu, Shaojun Wei: Multibank memory optimization for parallel data access in multiple data arrays. ICCAD 2016: 32
    [c]  Shouyi Yin, Xianqing Yao, Tianyi Lu, Leibo Liu, Shaojun Wei: Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory. ICCAD 2016: 127
    [c]  Peng Ouyang, Shouyi Yin, Chunxiao Xing, Leibo Liu, Shaojun Wei: Energy management on DVS based coarse-grained reconfigurable platform. NANOARCH 2016: 49-54